1. Field of the Invention
The present invention relates to an SR flip-flop.
2. Description of the Related Art
In digital circuits, SR flip-flops are widely employed. An SR flip-flop includes a set terminal and a reset terminal, and is configured to output, via its output terminal, an output signal that corresponds to a set signal and a reset signal input to the set terminal and the reset terminal. When the set signal is asserted (set to high level, for example), the SR flip-flop sets a positive logic output (which will be referred to as “non-inverted output”, or otherwise simply as “output”) Q to a first level (e.g., high level) at each positive edge timing of the set signal. When the reset signal is asserted, the SR flip-flop sets the output Q to a second level (e.g., low level) at each positive edge timing of the reset signal. The SR flip-flop is configured to output an inverted output #Q that is obtained by logical inversion of the output Q, in addition to the output Q.
Typical examples of such an SR flip-flop include: a NOR SR flip-flop including two cross-connected NOR (logical NOR) gates; and a NAND SR flip-flop including two cross-connected NAND (logical NAND) gates.
With such a NOR SR flip-flop or a NAND SR flip-flop, when the set terminal and the reset terminal are asserted at the same time, the positive logic output and the inverted output have the same level. In order to solve such a problem, such an input operation in which the set terminal and the reset terminal are asserted at the same time is inhibited.
Also, a set priority flip-flop and a reset priority flip-flop are known, which are configured such that, when the set terminal and the reset terminal are asserted at the same time, one of the two logic states is prioritized.
[Related Art Documents]
[Patent Documents]
    [Patent Document 1]
U.S. Pat. No. 6,657,472B1 Specification    [Patent Document 2]
U.S. Pat. No. 5,710,744 Specification
Such an SR flip-flop is employed in a semiconductor test apparatus shown in FIG. 1 of Patent document 2, for example. Such a flip-flop employed in such a semiconductor test apparatus is required to permit simultaneous assertion in which the set terminal and the reset terminal are asserted at the same time. Accordingly, there is a need to employ a set priority flip-flop or otherwise a reset priority flip-flop. However, with conventional set priority flip-flops or reset priority flip-flops, the prioritized input terminal is fixed. That is to say, once it is designed, the prioritized input terminal cannot be changed, which is a restriction in the design.